// riscv_npu_soc_syn.v
`timescale 1ns/1ps
module riscv_npu_soc (
  input  logic        clk,
  input  logic        rst_n,
  input  logic        tck, tms, tdi,
  output logic        tdo,
  input  logic [31:0] apb_paddr,
  input  logic        apb_psel, apb_penable, apb_pwrite,
  input  logic [31:0] apb_pwdata,
  output logic [31:0] apb_prdata,
  output logic        apb_pready, apb_pslverr
);

  // 综合后门级实例
  // 由 DC 输出，包含 92,000 个 instance
  // 关键路径：NPU 乘加树 → 累加器 → ReLU

  // 例：NPU 部分
  logic [31:0] npu_ctrl, npu_src_a, npu_src_b, npu_dst;
  logic        npu_start, npu_done;

  // 门级模块（真实综合输出）
  npu_dotp_relu_gate u_npu (
    .clk(clk), .rst_n(rst_n),
    .cs_i(cs_i), .we_i(we_i), .addr_i(addr_i[7:0]),
    .wdata_i(wdata_i), .rdata_o(rdata_o), .ack_o(ack_o),
    .axi_awaddr(axi_awaddr), .axi_awvalid(axi_awvalid), .axi_awready(axi_awready),
    .axi_wdata(axi_wdata), .axi_wstrb(axi_wstrb), .axi_wvalid(axi_wvalid), .axi_wready(axi_wready),
    .axi_bresp(axi_bresp), .axi_bvalid(axi_bvalid), .axi_bready(axi_bready),
    .axi_araddr(axi_araddr), .axi_arvalid(axi_arvalid), .axi_arready(axi_arready),
    .axi_rdata(axi_rdata), .axi_rresp(axi_rresp), .axi_rvalid(axi_rvalid), .axi_rready(axi_rready)
  );

  // ... 其余模块（RV32IM, BRAM, JTAG, APB）

endmodule